Embodiments herein generally relate to signal phase synchronizer systems and methods. Phase lock loops (PLLs) are conventionally used to synchronize the frequency of signals. Such phase lock loops dynamically lock the frequency of a generated signal to an external repetitive reference signal. Phase lock loops use a phase detector to determine whether a feedback signal edges earlier or later than a reference signal edge. The phased detector logic generates “earlier” and “later” signals that are pulse-width modulated, widening as time separation increases. Though they are digital, those signals cannot immediately be used for control. Analog circuitry must filter and integrate such signals before the phase lock loops can dynamically lock the frequency of the signals. Thus, conventional phase lock loop circuits utilize an analog control voltage that adjusts an oscillator to yield the desired output frequency.